IO Layout Engineer

ACL Digital

Company: ACL Digital
Salary: Not Mentioned
Location: Bengaluru, Karnataka, IN
Experience: 3+ Years
Qualification: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical Engineering, or VLSI

Overview AI Summary

This opportunity at ACL Digital in Bengaluru calls for a skilled IO Layout Engineer to play a crucial role in the custom layout team. The position involves the detailed design and implementation of IO cells, ESD protection circuits, and high-voltage interfaces for cutting-edge ASIC/SoC applications, leveraging deep submicron and FinFET technologies. Candidates will work on critical aspects like ESD compliance, latch-up prevention, and physical verification, ensuring robust and reliable silicon designs. The ideal candidate will possess a strong foundation in VLSI and semiconductor design, with at least three years of specialized experience in IO or ESD layout. Expertise in Cadence Virtuoso and familiarity with industry-standard physical verification tools are essential. A deep understanding of process technologies, layout-dependent effects, and reliability constraints will be key to success in this challenging role. This position offers a chance to contribute to advanced semiconductor projects, working alongside circuit designers and other engineering teams to bring next-generation chips to life. It's an excellent pathway for professionals looking to deepen their expertise in physical design, integrate complex IO structures, and master the nuances of state-of-the-art IC manufacturing processes.

Job Description

Overview

ACL Digital is actively seeking a highly motivated and experienced IO Layout Engineer to join its custom layout team based in Bangalore. This role is central to the full-custom layout of IO cells, critical ESD protection structures, and high-voltage interfaces for advanced ASIC/SoC applications, utilizing deep submicron and FinFET technologies.

Key Responsibilities

Execute transistor-level custom layout for a diverse range of IO cell types, including standard IOs (CMOS, LVTTL, LVCMOS, SSTL, HSTL) and high-speed/specialty IOs (DDR, USB, PCIe, HDMI).
Implement ESD structures, develop comprehensive pad rings, and design protection circuits.
Collaborate closely with IO circuit designers to accurately translate schematics and design intent into physical layouts.
Ensure robust layout practices are applied to guarantee ESD compliance, prevent latch-up, manage electromigration (EM), and plan for effective voltage isolation and guard rings.
Verify layouts against foundry-specific design rules (DRC, LVS, antenna rules) and achieve physical verification closure (DRC, LVS, ERC, ANT) using industry-standard tools.
Participate in the floorplanning of the IO ring and its seamless integration with both analog and digital blocks.
Coordinate with packaging, ESD, and reliability engineering teams to support successful silicon tapeout.

Required Skills

Minimum of 3 years of hands-on experience specializing in IO and/or ESD layout.
Strong foundational understanding of ESD protection concepts and effective latch-up avoidance techniques.
Proficiency in using Cadence Virtuoso for advanced layout design and implementation.
Experience with leading physical verification tools such such as Calibre, Assura, or PVS.
Familiarity with advanced process technologies, including 28nm, 16nm, 7nm, and FinFET.
Solid knowledge of layout-dependent effects (LDE), IR drop analysis, and overall reliability constraints in integrated circuit design.
Exceptional attention to detail coupled with strong debugging and problem-solving abilities.

Eligibility

Candidates must hold a B.E/B.Tech or M.E/M.Tech degree in Electronics, Electrical Engineering, or VLSI.
A minimum of 3 years of relevant industry experience is required.

Preferred Skills

Experience in designing high-voltage or multi-voltage IO layouts (e.g., 1.8V/3.3V/5V interfaces).
Prior involvement in IO ring planning and integration within complex System-on-Chip (SoC) floorplans.
Understanding of power grid design, bump/ball map coordination, and ESD co-design principles.
Scripting capabilities in languages like SKILL, Tcl, or Python for layout automation tasks.