IT
Staff Engineer: Physical Design
Micron Technology
- Company
- Micron Technology
- Salary
- Not Mentioned
- Location
- India
- Experience
- Senior level (typically 8+ years)
- Qualification
- B.E/B.Tech/M.E/M.Tech in Electronics, VLSI, or Electrical Engineering
Overview AI Summary
The Staff Physical Design Engineer position at Micron Technology is a high-impact technical leadership role focused on bringing cutting-edge memory and system-level silicon products to life. Candidates will be responsible for navigating complex backend VLSI challenges, executing layout tasks from floorplanning through to final sign-off physical verification. This role is ideal for a seasoned semiconductor professional who thrives in a collaborative environment and has a proven track record of successful tape-outs at advanced nodes. Micron offers an exceptional platform for growth, putting you at the center of the global memory revolution while working with advanced engineering tools and methodologies.
Job Description
Overview
Micron Technology is seeking an experienced and highly skilled Staff Physical Design Engineer to join our innovative engineering team in India. This role focuses on driving physical design implementation for next-generation semiconductor and memory solutions. The successful candidate will lead complex block-level and full-chip design closures, ensuring optimal power, performance, and area (PPA) parameters are met.
Key Responsibilities
- Lead the physical design implementation process, including floorplanning, placement, clock tree synthesis (CTS), and routing.
- Execute sign-off physical verification (DRC/LVS) and electrical rule checks (ERC).
- Manage timing closure, cross-talk analysis, and static timing analysis (STA) across multiple PVT corners.
- Collaborate closely with architectural, synthesis, DFT, and custom layout teams to resolve design bottlenecks.
- Establish and optimize physical design flows, incorporating automation scripts to boost team productivity.
Required Skills
- Extensive hands-on experience with EDA tools from Synopsys (ICC2, PrimeTime) or Cadence (Innovus, Tempus).
- Strong command over static timing analysis (STA) and timing constraints formulation (SDC).
- Proficient in scripting languages like TCL, Python, or Perl for automated physical design flows.
- Comprehensive understanding of deep sub-micron process technologies (e.g., 7nm, 5nm, and below).
Eligibility
- Bachelor’s or Master’s degree in Electronics Engineering, VLSI Design, Electrical Engineering, or a related technical discipline.
- Demonstrated track record in physical design implementation with a deep understanding of chip layout challenges.
Key Skills
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